Array substrate, manufacturing method thereof, and display device

ABSTRACT

Embodiments of the invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises: a base substrate; a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a source electrode, a drain electrode and a pixel electrode formed on the gate insulating layer, wherein the pixel electrode is directly connected to the drain electrode; and an active layer formed on the gate insulating layer, the source electrode and the drain electrode.

TECHNICAL FIELD

Embodiments of the invention relate to an array substrate, amanufacturing method thereof and a display device.

BACKGROUND

With reference to FIG. 1 and 2, an array substrate of a conventionalTFT-LCD (Thin Film Transistor-Liquid Crystal Display) comprises: a gateline 11′ and a gate electrode 2′ formed on the base substrate 1′; a gateinsulating layer 3′ formed on the gate line 11′ and the gate electrode2′; an active layer 7′, a source electrode 4′ and a drain electrode 5′formed on the gate insulating layer 3′; a passivation layer 8′ formed onthe active layer 7′, the source electrode 4′ and the drain electrode 5′;a through hole 9′ formed in the passivation layer 8′; and a pixelelectrode 6′ formed on the passivation layer 8′. The pixel electrode 6′is connected to the drain electrode 5′ via the through hole 9′. Thisarray substrate is widely adopted due to its good controllability andthe like.

However, this array substrate has the following problems.

The through hole 9′ for connecting the pixel electrode 6′ and the drainelectrode 5′ is within the pixel region of the array substrate, and theregion for the through hole 9′ is opaque. Thereby, the aperture ratio ofthe array substrate is adversely influenced.

In the thin film transistor with top gate structure, the active layermay be undesirably irradiated by the light from a backlight.Accordingly, the thin film transistor with bottom gate structure isgenerally adopted in the array substrate. In the thin film transistorwith the bottom gate structure, the source and the drain electrodes andthe gate electrode are disposed on opposing sides of the active layer,as shown in FIG. 2. When the gate electrode 2′ is switched on, a currentpassage C′ is formed on the bottom side of the active layer 7′ so thatthe current passage C′ and the source and drain electrodes are separatedby a region corresponding to the thickness of the active layer 7. Sincethe conductivity of the active layer 7′ is relatively low, theproperties of the TFT may be reduced in the case that the current passesthrough the region separating the current passage C′ and the source anddrain electrodes.

SUMMARY

According to an aspect of the invention, an array substrate is provided.The array substrate comprises:

-   a base substrate;-   a gate line and a gate electrode formed on the base substrate;-   a gate insulating layer formed on the gate line and the gate    electrode;-   a source electrode, a drain electrode and a pixel electrode formed    on the gate insulating layer, wherein the pixel electrode is    directly connected to the drain electrode; and-   an active layer formed on the gate insulating layer, the source    electrode and the drain electrode.

For example, each of the source electrode and the drain electrodecomprises at least two conductive layers.

For example, each of the source electrode and the drain electrodecomprises a transparent electrode layer and a metal layer provided onthe transparent electrode layer, the pixel electrode and the transparentelectrode layer are formed integrally.

For example, the array substrate further comprises:

-   a passivation layer formed on the source electrode, the drain    electrode and the active layer, wherein a through hole is formed in    the passivation layer; and-   a data line formed on the passivation layer, wherein the data line    is connected to the source electrode via the through hole.

For example, the array substrate further comprises: an ohmic contactlayer which is formed between the source electrode and the active layeras well as between the drain electrode and the active layer.

According to another aspect of the invention, a manufacturing method ofan array substrate is provided. The method comprises:

-   forming a gate line and a gate electrode on a base substrate;-   forming a gate insulating layer on the gate line and the gate    electrode;-   forming a conductive layer on the gate insulating layer, and    performing a patterning process on the conductive layer to form a    drain electrode, a source electrode and a pixel electrode, wherein    the pixel electrode is directly connected to the drain electrode;    and-   forming an active layer on the gate insulating layer, the source    electrode and the drain electrode.

For example, the step of forming the drain electrode, the sourceelectrode and the pixel electrode comprises: sequentially forming atleast two conductive layers on the gate insulating layer, and performinga patterning process on the at least two conductive layers to form thesource electrode, the drain electrode and the pixel electrode.

For example, the step of forming the drain electrode, the sourceelectrode and the pixel electrode comprises: sequentially forming twoconductive layers on the gate insulating layer, and performing apatterning process on the two conductive layers to form the sourceelectrode, the drain electrode and the pixel electrode. The twoconductive layers are a transparent electrode layer and a metal layerprovided on the transparent electrode layer, each of the sourceelectrode and the drain electrode is formed by the transparent electrodelayer and the metal layer, and the pixel electrode is merely formed bythe transparent electrode layer.

For example, the method further comprises:

-   forming a passivation layer on the source electrode, the drain    electrode and the active layer;-   forming a through hole in the passivation layer;-   forming a data line on the passivation layer, wherein the data line    is connected to the source electrode via the through hole.

For example, the method further comprises: forming an ohmic contactlayer between the source electrode and the active layer as well asbetween the drain electrode and the active layer.

According to still another aspect of the invention, a display device isprovided. The display device comprises the above-mentioned arraysubstrate.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to clearly illustrate the technical solution of the embodimentsof the invention, the drawings of the embodiments will be brieflydescribed in the following; it is obvious that the described drawingsare only related to some embodiments of the invention and thus are notlimitative of the invention.

FIG. 1 is a plane view illustrating a conventional array substrate;

FIG. 2 is a sectional view illustrating the conventional arraysubstrate;

FIG. 3 is a plane view illustrating an array substrate according to thean embodiment of the invention;

FIG. 4 is a sectional view illustrating the array substrate according tothe embodiment of the invention;

FIG. 5-FIG. 8 are schematic views illustrating a manufacturing method ofan array substrate according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In order to make objects, technical details and advantages of theembodiments of the invention apparent, the technical solutions of theembodiment will be described in a clearly and fully understandable wayin connection with the drawings related to the embodiments of theinvention. It is obvious that the described embodiments are just a partbut not all of the embodiments of the invention. Based on the describedembodiments herein, those skilled in the art can obtain otherembodiment(s), without any inventive work, which should be within thescope of the invention.

With reference to FIG. 3 and 4, an array substrate according to anembodiment of the invention comprises:

-   a base substrate 1;-   a gate line 11 and a gate electrode 2 formed on the base substrate    1;-   a gate insulating layer 3 formed on the gate line 11 and the gate    electrode 2;-   a source electrode 4, a drain electrode 5 and a pixel electrode 6    formed on the gate insulating layer 3, wherein the pixel electrode 6    is directly connected to the drain electrode 5; and-   an active layer 7 formed on the gate insulating layer 3, the source    electrode 4 and the drain electrode 5.

For example, each of the source electrode 4 and the drain electrode 5comprises at least two conductive layers.

For example, each of the source electrode 4 and the drain electrode 5comprises a transparent electrode layer A and a metal layer B providedon the transparent electrode layer. The pixel electrode 6 and thetransparent electrode layer A are formed integrally.

For example, the array substrate further comprises:

-   a passivation layer 8 formed on the source electrode 4, the drain    electrode 5 and the active layer 7, wherein a through hole 9 is    formed in the passivation layer 8; and-   a data line 10 formed on the passivation layer 9, wherein the data    line 10 is connected to the source electrode 4 via the through hole    9.

Alternatively, the data line 10 is provided in the same layer as thesource electrode 4 and directly connected to the source electrode 4, andin this case, the passivation layer 8 formed on the source electrode 4,the drain electrode 5 and the active layer 7 as well as the through hole9 may be omitted. However, it should be noted that, a short circuit mayeasily occur between the data line 10 and the pixel electrode 6 in thecase that the data line 10 is provided in the same layer as the pixelelectrode 6.

For example, the array substrate may further comprise an ohmic contactlayer (not shown) formed between the source electrode 4 and the activelayer 7 as well as between the drain electrode 5 and the active layer 7.The ohmic contact layer may be a doped layer (for example, an N⁺ a-Silayer). The contact resistance between the source and drain electrodesand the active layer can be decreased by forming such ohmic contactlayer, and thereby the properties of the TFT can be improved.

In the array substrate according to the embodiment of the invention, thepixel electrode is connected to the drain electrode directly, thethrough hole (if it is foamed) for connecting the data line and thesource electrode is provided in the region for the data line, thus theaperture ratio of the array substrate can be increased. Furthermore, inthe array substrate according to the embodiment of the invention, thesource and drain electrodes are provided on the same side of the activelayer as the gate electrode, thus the source and drain electrodes areconnected to the current passage C (only a portion of the currentpassage C is shown in the drawings) directly so that the properties(such as, conductivity and the like) of the TFT can be improved.

With reference to FIG. 5 to FIG. 8, a manufacturing method of an arraysubstrate according to an embodiment of the invention comprises thefollowing steps.

Step S1, a gate line 11 and a gate electrode 2 are formed on a basesubstrate 1;

As shown in FIG. 5, a gate metal layer is deposited on the basesubstrate 1, and the gate line 11 and the gate electrode 2 are formed byperforming a patterning process on the gate metal layer. The gate metallayer may be formed of Cr, Mo, Al, Cu, W, Nd or an alloy thereof.

Step S2, a gate insulating layer 3 is deposited after the Step S1, aconductive layer is formed on the gate insulating layer, and then asource electrode 4, a drain electrode 5 and a pixel electrode 6 areformed by performing a pattering process on the conductive layer.

For example, the conductive layer comprises at least two conductivelayers that are formed on the gate insulating layer sequentially.

For example, the conductive layer comprises two conductive layers thatare formed on the gate insulating layer sequentially. The two conductivelayers are a transparent electrode layer A and a metal layer B providedon the transparent electrode layer A. In this case, the patterningprocess is performed on the transparent electrode layer A and the metallayer B to form the source electrode 4, the drain electrode 5 and thepixel electrode layer 6. The transparent electrode layer A may be madeof a transparent conductive oxide, such as ITO or IZO. The metal layer Bmay be formed of Cr, Mo, Al, Cu, W, Nd or an alloy thereof. As shown inFIG. 6, each of the source electrode 4 and the drain electrode 5comprises the transparent electrode layer A and the metal layer B, thepixel electrode 6 and the transparent electrode layer A are formedintegrally so that the pixel electrode 6 is connected to the drainelectrode 5 directly. As the stacked structure of the transparentelectrode layer A and the metal layer B only exist in the TFT region andthe pixel region is only provided with the transparent electrode layerA, thus the light transmission in the pixel region is not affected.

For example, the source electrode 4, the drain electrode 5 and the pixelelectrode 6 may be formed by one patterning process with a half-tonemask or a gray-tone mask.

For example, the source electrode 4, the drain electrode 5 and the pixelelectrode 6 may be formed by two patterning processes with normal masks.

Step S3, an active layer 7 is formed on the gate insulating layer 3, thesource electrode 4 and the drain electrode 5.

As shown in FIG. 7, a semiconductor layer is deposited after the StepS2, and the active layer 7 is formed by performing a patterning processon the semiconductor layer.

Step S4, a passivation layer 8 is formed on the source electrode 4, thedrain electrode 5 and the active layer 7, and a through hole 9 is formedin the passivation layer 8 by performing a patterning process on thepassivation layer 8;

As shown in FIG. 8, a passivation film is deposited after the Step S3,then the passivation film is patterned to remove the passivation film inthe region other than the regions of the source electrode 4, the drainelectrode 5 and the active layer 7 and in the region for forming thethrough hole, so that the passivation layer 8 and the through hole 9 areformed. The source electrode 4 is exposed by the through hole 9.

Step S5, a metal layer is deposited on the passivation layer 8, and thenthe metal layer is patterned to form a data line 10.

The data line 10 is connected to the source electrode 4 via the throughhole 9 (as shown in FIG. 4).

Alternatively, the Step S4 and Step S5 may be omitted, and in this case,the data line and the source and drain electrodes may be formedsimultaneously in Step S2 and the data line is connected to the sourceelectrode directly. However, a short circuit may easily occur betweenthe data line and the pixel electrode in the case that the data line isprovided in the same layer as the pixel electrode.

As described above, each of the source and drain electrodes is formed bythe stacked structure comprising the transparent electrode layer A andthe metal layer B, the resistance of the stacked structure actually isthe parallel resistance of the metal layer and the transparent electrodelayer for forming the source and drain electrodes, and such parallelresistance is lower than the resistance of the source and drainelectrodes merely formed by the metal layer B. Accordingly, theconductivity of the source can drain electrodes can be increased, andthe properties of TFT can be improved.

In addition, an ohmic contact layer (for example, the ohmic contactlayer is formed by a doped layer, such as an N⁺ a-Si layer)) may beformed between the source electrode and the active layer as well asbetween the drain electrode and the active layer to decrease the contactresistance between the source and drain electrodes and the active layer.in this case, one additional patterning process should be employed.

According to an embodiment of the invention, a display device is furtherprovided. The display device comprises any one of the above describedarray substrates.

The foregoing are only preferable embodiments of the invention. It is tobe noted that, those with ordinary skills in the art may make variousmodifications and changes without departing the technical principle ofthe invention, and these modifications and changes should be deemed tobe within the protection scope of the invention.

What is claimed is:
 1. A manufacturing method of an array substrate,comprising: forming a gate line and a gate electrode on a basesubstrate; forming a gate insulating layer on the gate line and the gateelectrode; forming a conductive layer on the gate insulating layer, andperforming a patterning process on the conductive layer to form a drainelectrode, a source electrode and a pixel electrode, wherein the pixelelectrode is directly connected to the drain electrode; and forming anactive layer on the gate insulating layer, the source electrode and thedrain electrode.
 2. The manufacturing method according to claim 1,wherein the step of forming the drain electrode, the source electrodeand the pixel electrode comprises: sequentially forming at least twoconductive layers on the gate insulating layer, and performing apatterning process on the at least two conductive layers to form thesource electrode, the drain electrode and the pixel electrode.
 3. Themanufacturing method according to claim 2, wherein the step of formingthe drain electrode, the source electrode and the pixel electrodecomprises: sequentially forming two conductive layers on the gateinsulating layer, and performing a patterning process on the twoconductive layers to form the source electrode, the drain electrode andthe pixel electrode, wherein the two conductive layers are a transparentelectrode layer and a metal layer provided on the transparent electrodelayer, each of the source electrode and the drain electrode is formed bythe transparent electrode layer and the metal layer, and the pixelelectrode is merely formed by the transparent electrode layer.
 4. Themanufacturing method according to claim 1, further comprising: forming apassivation layer on the source electrode, the drain electrode and theactive layer; forming a through hole in the passivation layer; forming adata line on the passivation layer, wherein the data line is connectedto the source electrode via the through hole.
 5. The manufacturingmethod according to claim 1, further comprising: forming an ohmiccontact layer between the source electrode and the active layer as wellas between the drain electrode and the active layer.